Content addressable memory storage device

ABSTRACT

Binary and ternary content addressable memory (CAM) cells are disclosed, which permit the construction of high-performance, large-capacity CAM arrays. The CAM cells have a reduced match line power dissipation, and a reduced compare line loading that is data independent, and full swing comparator output. Match line power dissipation is limited by means of a NAND chain match line. Loading on compare lines is limited by connecting compare lines to the gate terminals of the CAM cell comparator. Local precharge devices at the output of the comparator provide full swing compare logic levels for faster matching. The same precharge devices also serve as an active reset for the comparator. Comparator circuits for ternary CAM cells further employ disable means, which makes the comparison operation conditional on the value stored in the mask memory element. The use of disable means allows the mask and data to be stored separately in a non-encoded form. As a result, mask and data information may be read and written independently of one another.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to content addressable memory (CAM), andmore specifically content addressable memory storage elements suitablefor constructing high-speed, large-capacity, binary or ternary CAMarrays.

2. Description of the Background Art

A content addressable memory (CAM) is a memory in which a group ofmemory elements are selected or identified by their content, rather thanby their physical location. A CAM includes a matrix of CAM cellsarranged in rows and columns. Each CAM cell includes compare logic, andstores one bit of digital information. One or more bits of informationconstitute a word. A content addressable memory compares a search word(comparand) with a set of words stored within the CAM. During thecompare operation, an indicator associated with each stored wordproduces a comparison result, indicating whether or not the search wordmatches the stored word.

FIG. 1 shows one particular binary CAM cell according to prior art,including a match logic circuit (transistors T2, T3 and T4), twotransistor access devices T0 and T1, and a memory element D0. The memoryelement D0 stores one bit of digital information. FIG. 2 shows a typicalimplementation of a static memory element D0 using two NMOS transistorsT2 and T3 and two PMOS transistors T0 and T1, according to prior art.The static memory element D0 has two states and two complementary cellnodes C and CN. In one state, C has a high signal level and CN has a lowsignal level, whereas in the other state, CN has a high level and C hasa low level. The two access devices T0 and T1 in FIG. 1 couple thememory element D0 to two complementary bit lines BL and BLN,respectively. The data access device T0 connects C to BL and the secondaccess device T1 connects CN to BLN. A word line WL connects togetherthe gate terminals of the two access devices T0 and T1. A comparatorhaving two transistor discharge devices T3 and T2 couples the two cellnodes C and CN respectively to two complementary compare linesdesignated as K and KN. The output of the comparator, designated as X,indicates the result of the comparison. The comparison results for anentire word in a binary CAM array are transmitted to a match line ML viathe match output device T4 in a wired-NOR configuration.

A binary CAM cell has three distinct modes of access by means of thefollowing operations; a read operation, a write operation and a compareoperation.

1) During the read operation, the signal level at WL (initially low) isasserted high, activating the two access devices T0 and T1. With WLhigh, the activated data access device T0 is conducting, and C iselectrically connected to BL. Similarly, when WL is high, an electricalconnection is made between CN and BLN via the second access device T1.Once such electrical connection is established, the one bit ofdifferential data stored in the memory element D0 of the CAM cell istransmitted or read out to the bit lines BL and BLN. After a readoperation, WL is returned low, de-activating the two access devices T0and T1, and thereby isolating the memory element D0 from the bit lines.Bit lines BL and BLN (initially precharged to a high state) are returnedto a precharged (reset) state following the read operation. FIG. 3 showsthe signal levels and timing for a typical read operation, according toprior art.

2) During the write operation, one bit of differential data is placed onthe bit lines BL and BLN. One state is asserted on BL and its complementis placed on BLN. WL (initially low) is asserted high, activating thetwo access devices T0 and T1. With WL high, the activated data accessdevice T0 is conducting, and C is electrically connected to BL.Similarly, an electrical connection is made between CN and BLN via thesecond access device T1. The differential data placed on the bit linesBL and BLN, is transmitted or written to the memory element D0 of theCAM cell for storage. Upon completion of a write operation, WL isreturned low, de-activating transistors T0 and T1, and thereby isolatingthe memory element D0 from the bit lines. Bit lines BL and BLN(initially precharged to high state) are returned to the precharged(reset) state following the write operation. FIG. 4 shows the signallevels and timing for the write operation.

3) For the compare operation, one bit of differential compare data isplaced on the compare lines K and KN. One state is asserted on K whileits complement is placed on KN. The comparator logic circuit determinesif the bit of compare data is equivalent to the data stored in thememory element D0. If K is equivalent to C in signal level, then thecomparator output node X is low and the match line ML (initiallyprecharged high) remains unaffected--indicating a match. If K is notequivalent to C, then the comparator output node X goes high to enableT4, and ML is pulled low--indicating a non-match (also called a "miss").For example, if both C and KN are high then an output node X of thecomparator is charged high through T3, activating the match outputdevice T4. Consequently, the wired-NOR match output at ML is pulled lowby T4, indicating a non-match. Similarly, if CN and K are both high thenthe output node X is charged high through T2, activating the pull downdevice T4. Subsequently, ML is pulled low indicating a non-match. Aftera compare operation, both compare lines K and KN are returned to a lowsignal level to discharge the comparator output node X through either T2or T3 depending on the state of the memory element D0. Discharging ofthe output node X resets the comparator discharge devices T2 and T3,disables T4 and allows ML to be precharged to a high state for the nextcompare operation. FIG. 5 shows typical signal levels and timing for thecompare operation, according to prior art.

There are several known approaches to CAM cells in the art. A journalpaper by Kenneth J. Schultz entitled "A Survey of Content-addressableMemory Cells" published in Integration, the VLSI Journal, Vol. 23, pp.171-188, 1997 describes several CAM cell designs and summarizes theadvantages and disadvantages of each. The CAM cell of FIG. 1 and othersimilar configurations in the art, have certain unfavourablecharacteristics for constructing high-performance, large-capacity CAMarrays such as the following:

1) The compare lines are typically connected to the source or drainterminals of the comparator circuit transistors, causing the comparelines to be heavily loaded resulting in higher power consumption, andslower search operations. It should also be noted that for a CAM cellsimilar to FIG. 1, the loading on the compare lines is data dependant,which means that the CAM must be designed for memory data patterns whichrepresent the worst case loading conditions. For example, if all CAMcells in the same column of the CAM array contain the same data, anon-match within the column would require one compare line to dischargeall the X nodes within the column. The result is an increased effectiveload on one of the compare lines.

2) The comparator output node X does not experience a full signal swing.The discharge devices T2 or T3 are unable to charge the output node X toa voltage equivalent to the full power supply voltage. As a result, thematch output device T4 is not completely turned on and the discharge ofthe match line ML is done at a slower rate, thereby slowing down thematching process. One could employ PMOS devices for the comparator tosolve this problem, however in doing so another problem is created. PMOSdevices would not be able to discharge the output node X completely,making the resetting of ML difficult if not impossible, since NMOS matchoutput transistor T4 would remain on.

3) The use of wired-NOR matching is also unfavourable due to excessivepower dissipation in the match lines. In wired-NOR matching, ML isdischarged for non-matches. In applications where the majority of wordsare expected to mis-match, this technique is overly inefficient. Anotherdisadvantage of using wired-NOR matching is that the rate of dischargeof ML depends on how many CAM cells in a word are non-matching. The peakpower demands of each mis-matched word is data dependant and the arraymust be designed according to memory patterns representing the worstcase conditions.

A dynamic-NAND match function is one approach known in the art forreducing match line power dissipation in CAM's. European PatentApplication, #98300490.4 published on Aug. 12, 1998 and correspondingU.S. Pat. No. 5,859,791 show a means for a dynamic NAND match in CAM's.A CAM cell employing a dynamic-NAND match reduces the power dissipationin CAM arrays permitting the construction of high-performance,large-capacity arrays. A journal paper by Kenneth J. Schultz entitled"25 MHz Fully-Parallel Content Addressable Memory", published in theJournal of Solid States Circuits, Vol. 23, pp 1690-1696, November 1998,shows how a dynamic NAND match reduces power dissipation in CAM's andgives evidence that high-performance, large-capacity CAM arrays arerealizable with this technique.

In view of the above discussion of prior art, there is clearly a needfor CAM cell configurations that demand relatively lower powerconsumption while offering a relatively faster match and searchoperation.

It is known in the art, that a column of CAM cells may be excluded fromthe search or compare operation by asserting both compare lines low (orhigh in some CAM cells). This however, does not provide masking on a percell basis. In order to exclude particular CAM cells from a search orcompare, an additional storage bit is required to represent more thantwo states. A third state representing a "don't care" or "masked" statemay be used to exclude the CAM cell from the search or compareoperation, by forcing the cell to match regardless of the appliedcomparand data, K and KN. Cells capable of storing a third state for perbit masking purposes are known in the art as ternary CAM cells.

In regards to a ternary CAM configuration, U.S. Pat. Nos. 5,319,590 and5,051,949 disclose the use of two storage bits and a compare logiccircuit per CAM cell to encode a "don't care" state. A "don't care"state excludes the CAM cell from comparison by forcing the CAM cell tomatch independent of the state of the inputs at the compare lines K andKN. The ternary CAM cell designs described in these two patents storedata and mask information in an encoded format. A problem with thisapproach is that during decoding, the masked data information is lostwhere masked data is read out as "0" or low state. Encoding alsorequires that both mask and data be written simultaneously. In thisrespect it is desirable to have a new CAM design that avoids the needfor encoding the information.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an improved contentaddressable memory (CAM) cell suitable for constructing high-speed andlarge-capacity binary or ternary CAM arrays. The present invention takesadvantage of one or more of the following design features in thedisclosed CAM cells:

(1) Bit lines are separated from the compare lines to reduce loading onboth the compare lines and bit lines, permitting the construction oflarger and faster CAM arrays. With separate compare and bit lines, thesearch operation can be performed without affecting precharge timing ofthe read/write operation. Furthermore, signal levels of the comparelines at the end of search operation do not have to coincide withprecharge levels for a read/write operation. The result is a CAM cellwith a bandwidth potential approaching twice that of a CAM cell withoutseparate bit and compare lines.

(2) Local amplification for the compare lines is provided through thegates of discharge devices. This way, loading on the compare lines isindependent of data stored in the CAM cells. In addition, loading on thecompare lines is reduced, since the compare lines are connected to thegate terminals of the comparator means rather than to the source ordrain terminals.

(3) Means for precharging the comparator output is provided, whichgenerates full swing logic levels and functions as a reset of thecomparator after a compare operation. Full swing logic levels at thecomparator output provide faster matching for wired-NOR or NANDmatching.

(4) In the case of a ternary CAM cell, means for disabling thecomparator are provided, thereby allowing one bit to represent the maskand the other bit to represent the data, without a requirement forspecial encoding of the mask and data. In this configuration, the maskand data information may be read and written from the storage cellsseparately and independently of one another. This way, data informationis not lost and may be retrieved with a normal read data operation.Furthermore, the mask and data bits may be read and written at differenttimes independently of one another.

In accordance with an aspect of this invention, there is provided acontent addressable memory cell comprising:

a) a memory element for storing a data bit, said memory element having acell node;

b) access means coupled to said memory element and to a bit line,wherein said access means is responsive to a word line for coupling saidcell node to said bit line during a change in signal level in said wordline in a first predetermined direction;

c) comparator means coupled to said cell node and to a compare line forperforming a comparison between signal levels at said cell node and saidcompare line, during a change in signal level in said compare line in asecond predetermined direction, and for providing a comparator outputindicative of said comparison; and

d) resetting means for resetting said comparator means subsequent tosaid comparison.

In an embodiment of this invention, the content addressable memory cellfurther comprises match means responsive to the comparator output,wherein said content addressable memory cell is a member of a pluralityof similarly formed content addressable memory cells accessing a matchline driven by respective said match means of each of the contentaddressable memory cells. Preferably, the match means for each one ofthe plurality of similar content addressable memory cells comprises alogic NAND device positioned in series with one another along the matchline. Alternatively, the match means for each one of the plurality ofsimilar content addressable memory cells comprises a logic NOR devicepositioned in parallel with one another between a power supply node andthe match line.

The memory element can contain a static memory device, a dynamic memorydevice, a non-volatile memory device, or a single-ended memory device.

A transistor circuit embodiment of this invention can have a combinationof the following configurations:

A) The access means comprises transistor means responsive to the wordline for coupling the cell node to the bit line.

B) The comparator means comprises a pair of a first and a secondtransistor means in a series configuration for coupling the cell node toa power supply node, wherein said first transistor means is responsiveto the compare line and said second transistor means is responsive tothe cell node.

C) The resetting means comprises transistor means responsive either tothe compare line for coupling the comparator output to a power supplynode, or to a precharge line for coupling the comparator output to apower supply node.

In accordance with another aspect of this invention, there is provided aternary content addressable memory cell comprising:

a) a data memory element for storing a data bit, said data memoryelement having a data cell node;

b) a mask memory element for storing a mask bit, said mask memoryelement having a mask cell node;

c) data access means coupled to said data memory element and to a databit line,

d) mask access means coupled to said mask memory element and to a maskbit line; wherein said data and mask access means are responsive to aword line for coupling said data and mask cell nodes to said data andmask bit lines respectively during a change in signal level in said wordline in a first predetermined direction;

e) comparator means coupled to said data and mask cell nodes and to acompare line for performing a comparison between signal levels at saiddata cell node and said compare line, during a change in signal level insaid compare line in a second predetermined direction, and for providinga comparator output indicative of said comparison; and

f) disable means responsive to said mask cell node for disabling saidcomparator output when the mask cell node has a predetermined signallevel.

In another embodiment of this invention, the content addressable memorycell further comprises match means responsive to the comparator output,wherein said content addressable memory cell is a member of a pluralityof similarly formed content addressable memory cells accessing a matchline driven by respective said match means of each of the contentaddressable memory cells.

Preferably, the match means for each one of the plurality of similarcontent addressable memory cells comprises a logic NAND devicepositioned in series with one another along the match line.Alternatively, the match means for each one of the plurality of similarcontent addressable memory cells comprises a logic NOR device positionedin parallel with one another between a power supply node and the matchline.

Furthermore, the ternary content addressable memory cell may compriseresetting means for resetting said comparator means subsequent to saidcomparison. The disable means may also comprise transistor means fordecoupling the comparator output from the comparator means.

A transistor circuit embodiment of the ternary content addressablememory cell can have a combination of the following configurations:

A) The comparator means comprises transistor means responsive to thecompare line for coupling the data cell node to the comparator output,and the disable means comprises transistor means responsive to acomplement of the compare line for coupling the mask cell node to thecomparator output.

B) The disable means comprises transistor means for either decouplingthe data cell node from the comparator means, shunting the comparatormeans, or shunting the logic NAND device when implemented within thematch line.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention will now be further describedwith references to the drawings wherein:

FIG. 1 illustrates a prior art content addressable memory cell;

FIG. 2 illustrates a prior art 4-transistor static memory element;

FIG. 3 illustrates signal levels and timing for a read operationrelevant to FIG. 1;

FIG. 4 illustrates signal levels and timing for a write operationrelevant to FIG. 1;

FIG. 5 illustrates signal levels and timing for a search operationrelevant to FIG. 1 wherein waveforms indicate a non-match;

FIGS. 6A and 6B illustrate a binary CAM cell according to a preferredfirst embodiment of the present invention;

FIG. 7 illustrates signal levels and timing for a read operationrelevant to FIG. 6B;

FIG. 8 illustrates signal levels and timing for a write operationrelevant to FIG. 6B;

FIG. 9 illustrates signal levels and timing for a compare operationrelevant to FIG. 6B, wherein waveforms indicate a non-match;

FIGS. 10A and 10B illustrate a ternary CAM core cell according to apreferred second embodiment of the present invention having individualdata and mask bits, PMOS precharge device, single NMOS disable device,and NMOS-NAND match device;

FIG. 11 illustrates signal levels and timing for a read data operationrelevant to FIG. 10B;

FIG. 12 illustrates signal levels and timing for write data operationrelevant to FIG. 10B;

FIG. 13 illustrates signal levels and timing for a read mask operationrelevant to FIG. 10B;

FIG. 14 illustrates signal levels and timing for a write mask operationrelevant to FIG. 10B;

FIG. 15 Illustrates signal levels and timing for a ternary compareoperation relevant to FIG. 10B;

FIG. 16 Illustrates a third embodiment of a ternary CAM cell havingsingle PMOS precharge device with separate precharge line, single NMOSdisable device, passive NMOS pull-down on comparator output node X, andNMOS-NAND match device;

FIG. 17 illustrates a fourth embodiment of a binary CAM cell, using PMOSprecharge device, passive NMOS pull-down on comparator output X, andPMOS-NOR match device;

FIG. 18 illustrates a fifth embodiment of a binary CAM cell, using PMOSprecharge device, active NMOS pull-down on comparator output X , andPMOS-NOR match device;

FIG. 19 illustrates a sixth embodiment of a binary CAM cell, using NMOSprecharge device, passive PMOS pull-up on comparator output node X, andNMOS-NOR match device;

FIG. 20 illustrates a seventh embodiment of a binary CAM cell, usingNMOS precharge device, active PMOS pull-up on comparator output node X,and NMOS-NOR match device;

FIG. 21 illustrates an eighth embodiment of a binary CAM cell, usingNMOS precharge device, passive PMOS pull-up on comparator output node X,and PMOS-NAND match device;

FIG. 22 illustrates a ninth embodiment a binary CAM cell, using NMOSprecharge device, active PMOS pull-up on comparator output node X, andPMOS-NAND match device;

FIG. 23 illustrates a ternary CAM cell design in accordance with a tenthembodiment of the present invention, having active PMOS prechargedevice, passive NMOS pull-down on comparator output node X, andNMOS-NAND match device;

FIG. 24 illustrates a binary CAM cell, using PMOS precharge device,active NMOS pull-down on comparator output node X, and NMOS-NAND matchdevice in accordance with an eleventh embodiment of the presentinvention;

FIG. 25 illustrates a twelfth embodiment of ternary CAM cell having PMOSprecharge device, single NMOS disable device, active NMOS pull-down forcomparator output X, and NMOS-NAND match device;

FIG. 26 illustrates a thirteenth embodiment of a ternary CAM cell havingPMOS precharge device, two NMOS disable devices, passive NMOS pull-downon comparator output node X, and NMOS-NAND match device;

FIG. 27 illustrates a fourteenth embodiment of a ternary CAM cell havingPMOS precharge device, two disable devices, active NMOS pull-down oncomparator output node X, and NMOS-NAND match device;

FIG. 28 illustrates a fifteenth embodiment of a ternary CAM cell havingPMOS precharge device, two NMOS disable devices, passive NMOS pull-downon comparator output node X, and NMOS-NAND match device;

FIG. 29 illustrates a sixteenth embodiment of a ternary CAM cell havingPMOS precharge device, single NMOS disable (shunt) device in NMOS-NANDchain, passive NMOS pull-down on comparator output node X, and NMOS-NANDmatch device;

FIG. 30 illustrates a seventeenth embodiment of a ternary CAM cellhaving PMOS precharge device, single NMOS disable (shunt) device inNMOS-NAND chain, active NMOS pull-down on comparator output node X, andNMOS-NAND match device;

FIG. 31 illustrates an eighteenth embodiment of a ternary CAM cellhaving NMOS precharge device, single PMOS disable (shunt) device inPMOS-NAND chain, passive PMOS pull-up on comparator output node X, andPMOS-NAND match device;

FIG. 32 illustrates a nineteenth embodiment of a ternary CAM cell havingPMOS-NAND match device and NMOS precharge device;

FIG. 33 illustrates a twentieth embodiment of a ternary CAM cell havingNMOS precharge device, single PMOS disable device, passive PMOS pull-upon compare output node (X), PMOS-NAND match device; and

FIG. 34 illustrates a twenty-first embodiment of a ternary CAM cellhaving NMOS precharge device, single PMOS disable device, active PMOSpull-up on compare output node (X), PMOS-NAND match device.

DETAILED DESCRIPTION OF THE INVENTION

A binary CAM cell in accordance with a first embodiment of the presentinvention is illustrated in FIGS. 6A and 6B. FIG. 6A illustrates thisembodiment in a block diagram, whereas FIG. 6B illustrate the sameembodiment in a circuit diagram.

In FIG. 6A a binary CAM cell is shown as having a memory element Dohaving a cell node C, access means 2, comparator means 3 having anoutput node X, resetting means 4 and match means 5. The access means 2,upon receiving an appropriate signal from a word line WL, couples thememory element D0 to a bit line BL for read and write operations. Thecomparator means 3, upon receiving an appropriate signal from a compareline K, performs a comparison between the signal levels at the cell nodeC and the compare line K, and provides a comparison result accordinglyat the comparator output node X. The resetting means 4, upon receivingan appropriate signal from a precharge line PRE, precharges thecomparator means to its initial state before the comparison operationwas performed.

FIG. 6B shows the binary CAM cell in a transistor circuit configuration.As shown in this figure, the access means 2 consists of two transistoraccess devices T0 and T1, the comparator means 3 consists of twotransistor discharge devices T2 and T3, the resetting means 4 consistsof two transistor precharge devices T4 and T5, and the match means 5consists of a transistor NAND match device T6. Also in FIG. 6B, theprecharge line PRE and the compare line K are the same. Here, the memoryelement D0 of the CAM cell stores one bit of digital information. As anexample for the memory element D0, a typical implementation of a staticmemory element is shown in FIG. 2, which uses two NMOS transistors T2and T3 and two PMOS transistors T0 and T1. This static memory element D0has two states and two complementary cell nodes C and CN. In one state,C has a high signal level and CN has a low signal level, whereas in theother state, CN is high and C is low. The two access devices T0 and T1in FIG. 6B couple the memory element D0 to two complementary bit linesBL and BLN, respectively. The data access device T0 connects C to BL andthe second access device T1 connects CN to BLN. A word line WL connectstogether the gate terminals of the two access devices T0 and T1. Acomparator having two discharge devices T3 and T2 couples the cell nodesC and CN respectively to two complementary compare lines K and KN. T2connects CN to a comparator output node X and T3 connects C to X. Thegate terminal of T2 is connected to KN and the gate terminal of T3 isconnected to K. The two precharge devices T4 and T5 are connected inseries from the power supply node to the comparator output nodedesignated as X. The gate terminal of T5 is connected to KN and the gateterminal of T4 is connected to K. The comparator output X indicates theresult of the compare operation for the CAM cell. The comparator outputnode X is connected to the gate terminal of the NAND match device T6.The NAND match device T6, in series with other match devices of the sameword, is used to combine compare information from all CAM cells within aword. This mechanism is used to determine if all CAM cells within a wordmatch a compare word.

In alternative embodiments to that shown in FIG. 6B, the gate terminalof T5 is connected to K, whereas the gate terminal of T4 is connected toKN.

The CAM cell, according to the first embodiment has three distinct modesof access by means of the following operations; a read operation, awrite operation and a compare operation.

1) During the read operation, the signal level at WL (initially low) isasserted high, activating the two access devices T0 and T1. With WLhigh, the activated data access device T0 is conducting, and C iselectrically connected to BL. Similarly, when WL is high, an electricalconnection is made between CN and BLN via the second access device T1.Once such electrical connection is established, the one bit ofdifferential data stored in the memory element D0 of the CAM cell istransmitted or read out to the bit lines BL and BLN. After a readoperation, WL is returned low, de-activating the two access devices T0and T1, and thereby isolating the memory element D0 from the bit lines.Bit lines BL and BLN (initially precharged to a high state) are returnedto a precharged state following the read operation. FIG. 7 shows thesignal levels and timing for a read operation as performed by theembodiment of FIG. 6B.

2) During the write operation, one bit of differential data is placed onthe bit lines BL and BLN. One state is asserted on BL and its complementis placed on BLN. WL (initially low) is asserted high, activating thetwo access devices T0 and T1. With WL high, the activated data accessdevice T0 is conducting, and C is electrically connected to BL.Similarly, an electrical connection is made between CN and BLN via thesecond access device T1. The differential data placed on the bit linesBL and BLN, is transmitted or written to the memory element D0 of theCAM cell for storage. Upon completion of a write operation, WL isreturned low, de-activating T0 and T1, and thereby isolating the memoryelement Do from the bit lines. Bit lines BL and BLN (initiallyprecharged to a high state) are returned to a precharged state followingthe write. FIG. 8 shows the signal levels and timing for the writeoperation

3) For the compare operation, one bit of differential compare data isplaced on the compare lines, K and KN. One state is asserted on K whileits complement is placed on KN. The compare logic determines if the bitof compare data is equivalent to the data stored in the memory elementD0. If K is equivalent to C in signal level, then the comparator outputX remains at an initially precharged high level--indicating a match. IfK is not equivalent to C, the comparator output X is pulledlow--indicating a non-match (or a "miss"). For example, if CN is low andKN is high, then the output node X (initially precharged) is dischargedthrough T2, de-activating the NAND match device T6. Similarly, if C islow and K is high then the output node X is discharged through T3,de-activating the NAND match device T6. At the end of the compareoperation, both compare line K and KN are returned to a low signal levelto precharge the output node X via precharge devices T4 and T5. When Kand KN are both low, T4 and T5 are conducting and bring the output nodeX to a high logic level. Precharging of the output node X resets thecomparator for the next compare operation. FIG. 9 shows the signallevels and timing for the compare operation.

A ternary CAM cell in accordance with a second embodiment of the presentinvention is illustrated in FIGS. 10A and 10B. FIG. 10A illustrates thisembodiment in a block diagram, whereas FIG. 10B illustrate the sameembodiment in a circuit diagram.

In FIG. 10A a ternary CAM cell is shown as having a data memory elementD0 and a mask memory element D1 for storing a data bit and a mask bit,and having a data and a mask cell nodes C0 and C1 respectively, data andmask access means 21 and 22, comparator means 13 having an output nodeX, resetting means 4, match means 5 and disable means 23. The data andmask access means 21 and 22, upon receiving an appropriate signal from aword line WL, respectively couple the memory elements D0 and D1 to adata bit line BL0 and a mask bit line BL1 for read and write operations.The comparator means 13, upon receiving an appropriate signal from acompare line K, performs a comparison between the signal levels at thecell node C0 and the compare line K, and provides a comparison resultaccordingly at the comparator output node X, provided that the mask bitstored in the mask memory element D1 is high. If the mask bit is low,however, the comparator output X is disabled by the disable means 23.The resetting means 4, upon receiving an appropriate signal from aprecharge line PRE, precharges the comparator means 13 to its initialstate before the comparison operation was performed.

FIG. 10B shows the ternary CAM cell in a transistor circuitconfiguration. As shown in this figure, the data access means 21consists of two transistor access devices T0 and T1, the mask accessmeans 22 consists of two transistor access devices T8 and T9, thecomparator means 13 consists of two transistor discharge devices T2 andT3, the resetting means 4 consists of two transistor precharge devicesT4 and T5, the disable means consists of a disable transistor device T7,and the match means 5 consists of a transistor NAND match device T6.Also in FIG. 10B, the precharge line PRE and the compare line K are thesame. Here, each of the data and mask memory elements D0 and D1 of theternary CAM cell store one bit of digital information. As an example forthe data memory element D0, a typical implementation of a static memoryelement is shown in FIG. 2, which uses two NMOS transistors T2 and T3and two PMOS transistors T0 and T1. This static memory element D0 hastwo states and two complementary cell nodes C and CN. In one state, Chas a high signal level and CN has a low signal level, whereas in theother state, CN is high and C is low. The two access devices T0 and T1in FIG. 10B couple the data memory element D0 to BL0 and BLN0. The dataaccess device T0 connects C0 to BL0 and the mask access device T1connects CN0 to BLN0. The additional two access devices T8 and T9 inFIG. 10B couple the mask memory element D1 to BL1 and BLN1. The thirdaccess device T8 connects C1 to BL1 and the fourth access device T9connects CN1 to BLN1. The comparator 13 having discharge devices T2 andT3 is similar to the comparator 3 of the above described binary CAMcell, shown in FIG. 6B. The two precharge devices T4 and T5 areconnected in series from the power supply node to the comparator outputnode X. The gate terminal of T4 is connected to K and the gate terminalof T5 is connected to KN. A disable device T7 connects the comparatoroutput node X to an intermediate node Y. The gate terminal of thedisable device T7 is connected to the C1 output of mask memory elementD1. The source terminals of T2 and T3 are both joined at theintermediate node Y. The drain terminals of T2 and T3 are respectivelyconnected to the CN0 and C0 outputs of the data memory element D0. T3connects C0 to the intermediate node Y and T2 connects CN0 to theintermediate node Y. The gate terminals of T2 and T3 are connected tothe KN and K lines respectively. The gate terminal of T2 is connected toKN and the gate terminal of T3 is connected to the K line. The output ofthe comparator X is connected to the gate terminal of the NAND chainmatch device T6. The disable device T7 shown in FIG. 10B allows thecomparator 13 to be enabled when the mask memory element D1 stores a "1"giving a high signal level at C1. When the mask memory element D1 storesa "0" so that C1 is low, the comparator pull down path is disconnected,thereby disabling the comparator 13.

In alternative embodiments to that shown in FIG. 10B, the gate terminalof T5 is connected to K, whereas the gate terminal of T4 is connected toKN.

The ternary CAM cell, according to the second embodiment has fivedistinct modes of access by means of the following operations: a readdata operation, a write data operation, a read mask operation, a writemask operation and a compare operation.

1) During the read data operation, the signal level at WL (initiallylow) is asserted high, activating the two access devices T0 and T1. WithWL high, the activated data access device T0 is conducting, and C0 iselectrically connected to BL0. Similarly, when WL is high, an electricalconnection is made between CN0 and BLN0 via the mask access device T1.Once such electrical connection is established, the one bit ofdifferential data stored in the data memory element D0 of the ternaryCAM cell is transmitted or read out to the two data bit lines BL0 andBLN0, which are initially precharged to a high state and are returned toa precharged high state following the read operation. FIG. 11 shows thesignal levels and timing for read operations.

2) During the write data operation, one bit of differential data isplaced on the two data bit lines BL0 and BLN0. One state is asserted onBL0 and its complement is placed on BLN0. WL (initially low) is assertedhigh, activating T0 and T1. With WL high, the activated data accessdevice T0 is conducting, and C0 is electrically connected to BL0.Similarly, an electrical connection is made between CN0 and BLN0 via themask access device T1. The differential data placed on the bit lines BL0and BLN0, is transmitted or written to the data memory element D0 of theternary CAM cell for storage. FIG. 12 shows the signal levels and timingfor the write data operation.

3) During the read mask operation, the signal level at WL is assertedhigh, activating T8 and T9. With WL high, the activated third accessdevice T8 is conducting, and C1 is electrically connected to BL1.Similarly, an electrical connection is made between CN1 and BLN1 via thefourth access device T9. Once electrical connection is established, theone bit of differential data stored in the mask memory element D1 of theternary CAM cell is transmitted or read out to the two mask bit linesBL1 and BLN1, which are initially precharged to a high state and arereturned to a precharged high state following the read operation. FIG.13 shows the signal levels and timing for the read mask operation.

4) During the write mask operation, one bit of differential data isplaced on the two mask bit lines BL1 and BLN1. One state is asserted onBL1 and its complement is placed on BLN1. WL (initially low) is assertedhigh, activating T8 and T9. With WL high, the activated third accessdevice T8 is conducting, and C1 is electrically connected to BL1.Similarity, an electrical connection is made between CN1 and BLN1 viathe fourth access device T9. The differential data placed on the maskbit lines BL1 and BLN1, is transmitted or written to the mask memoryelement D1 of the ternary CAM cell for storage. FIG. 14 shows the signallevels and timing for the write mask operation.

The mask and data operations occur independently of one another and maybe executed simultaneously. Four legitimate combinations of operationsmay occur simultaneously as follows:

a) Read Data, Read Mask

b) Read Data, Write Mask

c) Write Data, Read Mask

d) Write Data, Write Mask

5) For the compare operation, one bit of differential compare data isplaced on the compare lines, K and KN. One state is asserted on K whileits complement is placed on KN. When enabled, the comparator logiccircuit determines if the bit of compare data is equivalent to the datastored in the data memory element D0 of the CAM cell. If the mask bitoutput C1 is low, the comparator 13 is disabled and the output node Xremains at an initially precharged high level, regardless of the stateof compare inputs K, and KN. A high logic level at the comparator outputnode X indicates a match for the ternary CAM cell compare operation. Ifthe mask bit output C1 is high, the comparator 13 is enabled. When thecomparator 13 is enabled, and if K is equivalent to C0 in signal level,then the comparator output X remains at an initially precharged highlevel--indicating a match. When the comparator 13 is enabled and if K isnot equivalent to C0, the comparator output X is pulled low--indicatinga non-match. For example, if the mask bit output C1 is high, and both C0and KN are high (CN0 is low) then the output node X (initiallyprecharged) is discharged through T2, de-activating the NAND matchdevice T6. Similarly, if the mask bit output C1 is high and CN0 and Kare both high (C0 is low) then the output node X is discharged throughT3, de-activating the NAND match device T6. Both compare lines K and KNare returned to a low signal level to complete the compare operation andto precharge the output node X through T4 and T5. Precharging of theoutput node X resets the comparator 13 for the next compare operation.FIG. 15 shows the relevant signal levels and timing for the compareoperation.

The circuit designs in FIGS. 6B and 10B are two preferred embodiments ofthe present invention and are presented for illustration purposes only.One reasonably skilled in the art can derive alternative embodimentswithout departing from the principles of the present invention, which isdefined in the claims. FIGS. 16-34 illustrate nineteen other possiblealternative embodiments of the present invention.

Alternative embodiments of the present invention include variouscombinations of the following design configurations.

1. Passive NMOS pull-down to discharge the output node X: (T2,T3) inFIGS. 16 and 17; (T4,T5) in FIGS. 23, 28 and 29; and (T6,T7) in FIG. 26.

2. Active NMOS pull-down to discharge the output node X: (T2,T3,T7,T8)in FIG. 18; (T4,T5,T6,T7) in FIGS. 25 and 30; (T6,T7,T8,T9) in FIG. 27;and (T2,T3,T4,T5) in FIG. 24.

3. Passive PMOS pull-up to charge the output node X: (T2,T3) in FIGS.19, 21; and (T4,T5) in FIGS. 31 and 33.

4. Active PMOS pull-up to charge the output node X: (T2,T3,T7,T8) inFIGS. 20 and 22; (T4,T5,T6,T7) in FIG. 32; and (T2,T3,T4,T5) in FIG. 34.

5. Two PMOS precharge (high) devices in series: (T4,T5) in FIGS. 17, 18;(T7,T8) in FIGS. 23, 24 and 29; (T9,T10) in FIG. 25; (T8,T9) in FIGS.26, 28 and 30, and (T10,T11) in FIG. 27.

6. Two NMOS precharge (low) devices in series: (T4,T5) in FIGS. 19, 20,21, 22; (T7,T8) in FIGS. 31, 33 and 34; and (T8,T9) in FIG. 32.

7. A single PMOS precharge (high) device with separate precharge line:T5 in FIG. 16.

8. A single NMOS precharge (low) device with separate precharge line:Not shown

9. PMOS-NAND match line: T6 in FIGS. 21, 22, 33 and 34; T9 in FIG. 31;and T11 in FIG. 32.

10. NMOS-NAND match line: T6 in FIGS. 16, 23, and 24; T11 in FIGS. 25and 30; T10 in FIGS. 26 and 28; T12 in FIG. 27; and T9 in FIG. 29.

11. PMOS-NOR match line: T6 in FIGS. 17 and 18.

12. NMOS-NOR match line: T6 in FIGS. 19 and 20.

13. NMOS disable device in the comparator: T7 in FIG. 16; T8 in FIG. 25;(T4,T5) in FIGS. 26 and 27; and (T6,T7) in FIG. 28.

14. PMOS disable device in the comparator: T9 in FIGS. 33 and 34.

15. NMOS disable device in a NAND-match line: T6 in FIG. 29; and T10 inFIG. 30.

16. PMOS disable device in a NAND-match line: T6 in FIG. 31; and T10 inFIG. 32.

17. Compare and Bit signals share the same lines: Not shown.

18. Disable device connected to C1 of mask memory element: FIGS. 16 and25 to 34.

19. Disable device connected to CN1 of mask memory element: Not shown.

20. Dynamic Storage elements: Not shown.

21. Non-volatile memory elements: Not shown. 22 Single ended memoryelements: Not shown.

23. Two word lines, one for mask, one for data: Not shown.

In the third embodiment shown in FIG. 16, a single precharge device T5is used, where a separate signal is employed and appropriately timed atthe precharge line PRE.

In the fifth and sixth embodiments shown in FIGS. 18 and 19respectively, the CAM cell employs wired-NOR matching with PMOS and NMOSmatch devices, respectively.

In the sixth embodiment shown in FIG. 19, NMOS precharge devices T4 andT5 is used where appropriate portions of the comparator circuits arePMOS devices.

In the eighth embodiment shown in FIG. 21, a PMOS-NAND match chain ofdevices T6 is employed instead of an NMOS-NAND match chain of devices.

In the fourteenth embodiment shown in FIG. 27, two disable devices T4and T5 are used in place of one, and may be placed elsewhere in thecomparator circuits.

In the sixteenth embodiment shown in FIG. 29, the disable device T6 isplaced in the NAND match chain rather than in the comparator. Thisapproach, however, requires more power due to unnecessary transitions inthe comparator (for masked bits) and increased loading in the NAND matchchain.

Of course, numerous variations and adaptations may be made to theparticular embodiments of the invention described above, withoutdeparting from the spirit and scope of the invention, which is definedin the claims.

What is claimed is:
 1. A content addressable memory cell comprising:amemory element for storing a data bit, said memory element having a cellnode; access means coupled to said memory element and to a bit line,wherein said access means is responsive to a word line for coupling saidcell node to said bit line during a change in signal level in said wordline in a first predetermined direction; comparator means coupled tosaid cell node and to a compare line for performing a comparison betweensignal levels at said cell node and said compare line, during a changein signal level in said compare line in a second predetermineddirection, and for providing a comparator output indicative of saidcomparison; and resetting means for resetting said comparator meanssubsequent to said comparison.
 2. A content addressable memory cell asdefined in claim 1, further comprising match means responsive to thecomparator output, wherein said content addressable memory cell is amember of a plurality of similarly formed content addressable memorycells accessing a match line driven by respective said match means ofeach of the content addressable memory cells.
 3. A content addressablememory cell as defined in claim 2, wherein the match means for each oneof the plurality of similar content addressable memory cells comprisesone of a corresponding plurality of logic NAND devices positioned inseries with one another along the match line.
 4. A content addressablememory cell as defined in claim 2, wherein the match means for each oneof the plurality of similar content addressable memory cells comprisesone of a corresponding plurality of logic NOR devices positioned inparallel with one another between a power supply node and the matchline.
 5. A content addressable memory cell as defined in claim 1,wherein the memory element comprises a static memory device.
 6. Acontent addressable memory cell as defined in claim 1, wherein thememory element comprises a non-volatile memory device.
 7. A contentaddressable memory cell as defined in claim 1, wherein the memoryelement comprises a single-ended memory device.
 8. A content addressablememory cell as defined in claim 1, wherein the memory element comprisesa dynamic memory device.
 9. A content addressable memory cell as definedin claim 1, wherein the access means comprises transistor meansresponsive to the word line for coupling the cell node to the bit line.10. A content addressable memory cell as defined in claim 1, wherein thecomparator means comprises transistor means responsive to the compareline for coupling the cell node to the comparator output.
 11. A contentaddressable memory cell as defined in claim 1, wherein the comparatormeans comprises a pair of a first and a second transistor means in aseries configuration for coupling the cell node to a power supply node,wherein said first transistor means is responsive to the compare lineand said second transistor means is responsive to the cell node.
 12. Acontent addressable memory cell as defined in claim 1, wherein theresetting means comprises transistor means responsive to the compareline for coupling the comparator output to a power supply node.
 13. Acontent addressable memory cell as defined in claim 1, wherein theresetting means comprises transistor means responsive to a prechargeline for coupling the comparator output to a power supply node.
 14. Acontent addressable memory cell as defined in claim 1, furthercomprising:a mask memory element for storing a mask bit, said maskmemory element having a mask cell node; and mask access means coupled tosaid mask memory element and to a mask bit line; wherein said maskaccess means is responsive to the word line for coupling said mask cellnode to said mask bit line during a change in signal level in said wordline in the first predetermined direction.
 15. A content addressablememory cell comprising:a) a data memory element for storing a data bit,said data memory element having a data cell node;a mask memory elementfor storing a mask bit, said mask memory element having a mask cellnode; data access means coupled to said data memory element and to adata bit line, mask access means coupled to said mask memory element andto a mask bit line; wherein said data and mask access means areresponsive to a word line for coupling said data and mask cell nodes tosaid data and mask bit lines respectively during a change in signallevel in said word line in a first predetermined direction; comparatormeans coupled to said data and mask cell nodes and to a compare line forperforming a comparison between signal levels at said data cell node andsaid compare line, during a change in signal level in said compare linein a second predetermined direction, and for providing a comparatoroutput indicative of said comparison; and disable means responsive tosaid mask cell node for disabling said comparator output when the maskcell node has a predetermined signal level.
 16. A content addressablememory cell as defined in claim 15, further comprising match meansresponsive to the comparator output, wherein said content addressablememory cell is a member of a plurality of similarly formed contentaddressable memory cells accessing a match line driven by respectivesaid match means of each of the content addressable memory cells.
 17. Acontent addressable memory cell as defined in claim 16, wherein thematch means for each one of the plurality of similar content addressablememory cells comprises one of a corresponding plurality of logic NORdevices positioned in parallel with one another between a power supplynode and the match line.
 18. A content addressable memory cell asdefined in claim 16, wherein the match means for each one of theplurality of similar content addressable memory cells comprises one of acorresponding plurality of logic NAND devices positioned in series withone another along the match line.
 19. A content addressable memory cellas defined in claim 18, wherein the disable means comprises transistormeans for shunting the logic NAND device.
 20. A content addressablememory cell as defined in claim 15, further comprising resetting meansfor resetting said comparator means subsequent to said comparison.
 21. Acontent addressable memory cell as defined in claim 20, wherein theresetting means comprises transistor means responsive to the compareline for coupling the comparator output to a power supply node.
 22. Acontent addressable memory cell as defined in claim 20, wherein theresetting means comprises transistor means responsive to a prechargeline for coupling the comparator output to a power supply node.
 23. Acontent addressable memory cell as defined in claim 15, wherein thedisable means comprises transistor means for decoupling the comparatoroutput from the comparator means.
 24. A content addressable memory cellas defined in claim 15, wherein the disable means comprises transistormeans for decoupling the data cell node from the comparator means.
 25. Acontent addressable memory cell as defined in claim 15, wherein thedisable means comprises transistor means for shunting the comparatormeans.
 26. A content addressable memory cell as defined in claim 15,wherein each of the data memory element and the mask memory elementcomprises a static memory device.
 27. A content addressable memory cellas defined in claim 15, wherein each of the data memory element and themask memory element comprises a non-volatile memory device.
 28. Acontent addressable memory cell as defined in claim 15, wherein each ofthe data memory element and the mask memory element comprises asingle-ended memory device.
 29. A content addressable memory cell asdefined in claim 15, wherein each of the data memory element and themask memory element comprises a dynamic memory device.
 30. A contentaddressable memory cell as defined in claim 15, wherein the data accessmeans comprises transistor means responsive to the word line forcoupling the data cell node to the data bit line, and the mask accessmeans comprises transistor means responsive to the word line forcoupling the mask cell node to the mask bit line.
 31. A contentaddressable memory cell as defined in claim 15, wherein the comparatormeans comprises transistor means responsive to the compare line forcoupling the data cell node to the comparator output.
 32. A contentaddressable memory cell as defined in claim 15, wherein the comparatormeans comprises a pair of a first and a second transistor means in aseries configuration for coupling the data cell node to a power supplynode, said first transistor means being responsive to the compare lineand said second transistor means being responsive to the data cell node.